Methods and arrangements to model an asynchronous interface

ABSTRACT

Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may then alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, changes to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.

FIELD OF INVENTION

The present invention is in the field of clock circuits. Moreparticularly, the present invention relates to methods and arrangementsto model behavior of an asynchronous interface.

BACKGROUND

The push for high speed computing has led to the development of highspeed, time-constrained, asynchronous links such as IBM's self-timedinterfaces (STIs). In fact, the STI has been implemented in IBM'slargest servers for several generations, providing successively improvedinput-output (I/O) subsystem bandwidth capacities. Time-constrained,asynchronous links are asynchronous data interfaces that transmit dataover parallel bit lines via independent clock signals that aresubstantially synchronized at times. In particular, time-constrained,asynchronous interfaces, sometimes referred to as elastic or semi-staticinterfaces, may guarantee synchronous behavior over a specified timeinterval to facilitate data transfers.

For purposes of the data transfers, the synchronous nature of theelastic interfaces is limited to a time interval following the initialtransmission and receipt of a test pattern of data. The test patterndata is examined to determine the timing relationship or skew patternbetween bits received via different bit lines of the bus. Thereafter,for the extent of the time interval, data crossing the interface may bepresumed to follow the same skew pattern. Receive logic identifies theskew pattern based upon the test pattern data and determines the timingrequired to synchronously capture subsequent data sent across the sameinterface.

Elastic interfaces make use of the knowledge that the change in phasebetween independently driven clocks will occur over time and that therate of change is fairly constant. In particular, clocks for the elasticinterface will stay reasonably in phase for the time interval and, thus,for that time interval, the clocks can be viewed as being effectivelysynchronous for data transfers. However, after the expiration of thetime interval, the elastic interface is asynchronous again.

When testing circuit performance with regards to communication across anelastic interface, circuit designers must verify that the circuit cantransfer data during the specified time intervals. Otherwise, thecircuit will not function properly.

To verify the circuit's performance, designers utilize circuitsimulators to simulate the circuit's performance prior to the investmentof large amounts of capital to build the circuit. Ideally, circuitsimulations accurately simulate every potentially problematic aspect ofthe circuit operation. The problem with current circuit simulators fromthe perspective of the elastic interface is that skew/jitter logic isemployed to model asynchronous behavior. The skew/jitter logic isnon-deterministic—i.e. the phase shift employed for a signal is alwaysnon-static. So skew/jitter logic cannot be used for elastic interfacesor other semi-static interfaces that require that the skew/jitterimposed remains static for a period of time.

The current solution for this problem is to employ a static skewpattern. This avoids the deficiency in circuit simulation of the elasticinterface. The static skew pattern simulates one skew pattern of theelastic interface, however, this solution fails to simulate asynchronousbehavior of the elastic interface at the expiration of the synchronoustime interval, which is a potentially problematic aspect of the circuitoperation.

SUMMARY OF THE INVENTION

The problems identified above are in large part addressed by methods andarrangements to model an asynchronous interface. One embodiment providesa method to model behavior of an asynchronous interface. The method mayinvolve generating a first pattern of skews for a number of bit lines ofthe asynchronous interface and applying the first pattern of skews tobits associated with the number of bit lines during a time interval.Furthermore, the method may apply a second pattern of skews tosubsequent bits associated with the number of bit lines after the timeinterval.

Another embodiment provides a system to model behavior of anasynchronous interface. The system may comprise a delay applicator toapply skews to bits crossing the asynchronous interface via a number ofbit lines. The system may also comprise a delay generator to generate afirst pattern of the skews for the number of bit lines during a timeinterval and to generate a second pattern of skews for subsequent bitscrossing the asynchronous interface via the number of bit lines afterthe time interval.

Another embodiment provides machine-accessible medium containinginstructions to model behavior of an asynchronous interface, which whenthe instructions are executed by a machine, cause said machine toperform operations. The operations may involve generating a firstpattern of skews for a number of bit lines of the asynchronous interfaceand applying the first pattern of skews to bits associated with thenumber of bit lines during a time interval. The operations may furtherinvolve applying a second pattern of skews to subsequent bits associatedwith the number of bit lines after the time interval.

BRIEF DESCRIPTION OF THE DRAWINGS

Advantages of the invention will become apparent upon reading thefollowing detailed description and upon reference to the accompanyingdrawings in which, like references may indicate similar elements:

FIG. 1 depicts an embodiment of system level circuit simulation tosimulate synchronous and asynchronous behavior of a 64-bitpoint-to-point bus between a processor and another chip;

FIG. 2 depicts an example of a timing diagram for transmission andreceipt of bits across an N-bit point-to-point bus such as the 64-bitpoint-to-point bus of FIG. 1;

FIG. 3 depicts an embodiment of a circuit simulation for application ofa skew to a bit line to simulate synchronous and asynchronous behaviorof a time-constrained, asynchronous interface;

FIG. 4 depicts an embodiment of a staged multiplexor to equate theprobabilities for selection of a skew from a set of seven differentpotential skews to model the behavior of a bit line of an elasticinterface; and

FIG. 5 depicts a flowchart of an embodiment to simulate synchronous andasynchronous behavior of bit lines of an asynchronous bus.

DETAILED DESCRIPTION OF EMBODIMENTS

The following is a detailed description of embodiments of the inventiondepicted in the accompanying drawings. The embodiments are in suchdetail as to clearly communicate the invention. However, the amount ofdetail offered is not intended to limit the anticipated variations ofembodiments, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the present invention as defined by the appended claims.The detailed descriptions below are designed to make such embodimentsobvious to a person of ordinary skill in the art.

Generally speaking, methods and arrangements to model an asynchronousinterface are contemplated. Embodiments include transformations, code,state machines or other logic to generate a skew pattern for asemi-static or time-constrained, asynchronous interface and employ theskew pattern in data transfers during a time interval in which theasynchronous interface. Embodiments may then alter the skew pattern atthe expiration of the time interval. In many embodiments, changes to theskew pattern may be substantially non-deterministic. In otherembodiments, changes to the skew pattern may follow a heuristic or otherdynamic or pre-determined pattern.

While specific embodiments will be described below with reference toparticular circuit or logic configurations, those of skill in the artwill realize that embodiments of the present invention mayadvantageously be implemented with other substantially equivalentconfigurations.

Turning now to the drawings, FIG. 1 depicts an embodiment of systemlevel circuit simulation 100 to simulate synchronous and asynchronousbehavior of a 64-bit point-to-point bus, buses 133 and 135, between aprocessor 105 and another chip 140. For instance, processor 105 maymodel behavior of one of IBM's PowerPC 970 processors and chip 140 maymodel, for example, behavior of a memory controller hub designed tooperate with processor 105.

Logic associated with transmission of data from processor 105 to chip140 may include a synch counter 107, delay applicators 109, delaygenerators 111, and transmitters 115 to implement a skew pattern in datatransmitted across 32-bit bus 133. In other embodiments, synch counter107, delay applicators 109, and delay generators 111 may reside on thereceiver-side of bus 133. In such embodiments, a skew pattern may beapplied to the initial receive latch of receivers 142 rather than theinitial send latch of transmitters 115. Furthermore, embodiments thatimplement a skew pattern on the send side may also model fullpropagation delays.

Synch counter 107 may count clock cycles of the time interval in whichthe clocks of bus 133 remain substantially in phase, referred to as asynch count, to facilitate generation of a new skew pattern uponexpiration of the time interval. In some embodiments, the time intervalmay vary in accordance with a margin of error associated with the timeinterval. In further embodiments, the synch count for the time intervalmay be reset upon transmission of a test pattern of data.

While the present embodiment illustrates synch counter 107 for the sendside of bus 133 and a synch counter 144 for the receive side of bus 133,other embodiments may utilize a single synch counter such as synchcounter 107 for both sides of bus 133. Further embodiments may utilizesynch counter 107 to indicate the end of a time interval for more thanone bus such as bus 133 and bus 135. In one embodiment, other logic isimplemented in place of synch counter 107 to generate a signalindicative of the end of a time interval for synchronized data transferacross an asynchronous bus like bus 133 and 135.

Delay applicators 109 may apply skews to data in 113 bits crossing theasynchronous interface via a number of bit lines of bus 133. In thepresent embodiment, several possible skews may be applied to each bitline so delay generators 111 may generate the skew pattern by selectinga signal from available signals for each bit line. In furtherembodiments, delay applicators 109 may apply skews to bits afterselection of the skew pattern by delay generators 111. In suchembodiments, for example, delay generators 111 may select skews for eachbit line of bus 133 and delay applicators 109 may then apply the skewpattern to bits being transmitted across bus 133.

Delay generators 111 may generate a first pattern of skews for bit linesof bus 133 during a time interval. In many embodiments, delay generators109 may generate an independent skew for each bit line of bus 133. Theskew patterns may be generated by selecting skewed signals from a rangeof predetermined skewed signals available from delay applicators 109.The range may comprise a range of feasible skews for bus 133. Forinstance, delay generators 109 may generate 32 random select signals,one for each bit line of bus 133, to select from delays input from delayapplicators 109. Then, upon receipt of an indication from synch counter107 that the time interval is ending or has ended, delay generators 111may generate new selection signals to modify the skew pattern forsubsequent bits crossing bus 133 to chip 140.

Transmitters 115 may comprise a simulation of physical layer devicesadapted to transmit bits across bus 133 to receivers 142. Similarly,receiver 142 may comprise a simulation of physical layer devices adaptedto receive the bits from transmitters 115. Depending upon the parametersof the simulation, transmitters 115 and receivers 142 may simulate idealor less ideal circuitry operation.

Synch counter 117, delay generators 119, and delay applicators 121comprise logic to apply a skew pattern to bits on the receive side ofbus 135. In other embodiments, chip 140 may comprise logic such as delayapplicators 109 and delay generators 111 to apply the skew pattern tobits prior to transmitting the bits across bus 135.

In the present embodiment, transmitters 150 transmit data across bus 135to receivers 123 without skews related to, e.g., differences intemperature and voltage between bit lines of the bus, differences inlength of the bit lines, or the like. In further embodiments, one ormore of these skews or other skews may be applied to the bits crossingbus 135 prior to transmission from chip 140.

Delay applicators 121 may receive the bits and add a number of differentskews to each bit between the overall minimum and maximum latenciesexpected for the bit lines of bus 135. Applying skews between theminimum and maximum skews at delay applicators 121 advantageously avoidsthe necessity, in some embodiments, of separate logic for modeling azero clock cycle skew.

Delay generators 119 may randomly select a skew pattern for the bitsfrom those provided by delay applicators 121 based upon an indicationfrom synch counter 117. The indication from synch counter 117 may berelated to the transmission of test pattern data across bus 135 and/orthe end of a substantially synchronous time interval for bus 135. Thendelay generators 119 may forward the bits to a skew pattern determiner129.

Synch counter 117 may perform a substantially similar function as synchcounter 107 for bus 135. In some embodiments, synch counter 117 maycomprise logic adapted to decrement a synch count from an initial numberto zero and, upon reaching zero, transmit a signal to delay generators119 to select a new skew pattern. In other embodiments, synch counter117 may comprise part of other logic designed for a different and/orrelated purpose.

Synch counter 125 may generate a signal to indicate the end of asubstantially synchronous time interval for data transfer across bus135. Synch counter 125 may comprise logic to simulate differencespotentially encountered between signals received at delay generators 119and signals received at skew pattern determiner 129. In otherembodiments, skew pattern generator 129 may receive signals to indicatethe end of substantially synchronous time intervals for data transferacross bus 135 from synch counter 117.

Skew pattern determiner 129 may receive an indication from synch counter125 to demark the end of a first time interval of substantiallysynchronous behavior. Skew pattern determiner 129 may then, in responseto receipt of a new test pattern of bits, determine a new skew patternfor data transferred across bus 135 during a second time interval ofsubstantially synchronous behavior. The new skew pattern may be storedin current skew pattern 127 and utilized to organize data receivedduring the second time interval.

Skew pattern determiner 129 may then apply the current skew pattern forthe bit lines during the second time interval of substantiallysynchronous behavior and transmit the data to other logic via data out131. Current skew pattern 127 may comprise memory or logic to maintainthe most recent valid skew pattern for the bits crossing bus 135.

Chip 140 may be a simulation of a companion chip for processor 105 suchas a memory controller hub, a host bridge, a snoop controller, or thelike. Synch counter 144, skew pattern determiner 146, and current skewpattern 148 may model receipt and interpretation of data received fromtransmitters 115 in a manner similar to that of synch counter 125, skewpattern determiner 129, and current skew pattern 127.

FIG. 2 depicts an example of a timing diagram 200 for transmission andreceipt of bits across a bus such as the 64-bit point-to-point bus ofFIG. 1. The timing diagram 200 depicts increments in skew delay inrelation to a series latches from latch 1 to latch N. The skewassociated with latch 1 may be, for instance, a single clock cycle ofdelay for bit lines marked with an ‘X’ in the column of latch 1. Inother embodiments, the skew associated with latch 1 may be a zero clockcycle delay to simulate no skew or a negative skew, depending upon thetime reference associated with the latches. In further embodiments,latches may represent two or more clock cycles of delay.

In the present embodiment, latch 1 represents a zero skew and eachsuccessive latch, 2 through N, represents the addition of a single clockcycle of delay. Thus, latch 2 represents a single clock cycle of delayand latch N represents a clock delay of N−1 clock cycles. For example,the ‘X’ in the row of bit line 1 is under latch one to indicate a zeroclock cycle delay for bits received via bit line 1 and the ‘X’ in therow of bit line N is in the latch 2 column to indicate that bitsreceived via bit line N will have a single clock cycle skew. Similarly,an ‘X’ in the latch 3 column indicates a skew of two clock cycles forbits received via bit line 2 and each ‘X’ in the latch 4 columnindicates skews of three clock cycles for bits received via bit lines 3and 4.

The combination of the clock skews for the bus comprising bit lines 1through N is an example of a skew pattern. The skew pattern may bedetermined by comparing the skew of bits of test pattern datatransmitted across the bus. For instance, the test pattern data on eachbit line may propagate through a series of latches until all the testpattern data is received. Once the test pattern data is received, therelative progression of the bits of the test pattern data through theseries of latches may indicate the skew pattern.

Turning now to FIG. 3, there is shown an embodiment of a circuitsimulation 300 for application of a skew to a bit line to simulatesynchronous and asynchronous behavior of a time-constrained,asynchronous interface. The circuit simulation 300 includes a synchcounter 310, a delay generator 330, and a delay applicator 340 to modelthe behavior. For instance, synch counter 310 is adapted to count anumber of cycles, a synch count, which may be the number of cycles thatsynchronous behavior is specified or guaranteed for the asynchronousinterface. The synch count is reset when test pattern data istransmitted across the asynchronous interface by producing a resetsignal 316. The reset signal 316 is produced in response to applicationof a logical one at an input 305, which is indicative of the test databeing sent.

The logical one is applied to an input of ‘OR’ logic 312. The secondinput of ‘OR’ logic 312 is the output signal 326 of synch counter 310,which remains a logical zero until the end of the synch count. Intervalcounter 320 may decrement the synch count down to zero or count fromzero to the synch count. In some embodiments, the synch count is fixed.In other embodiments, the synch count, which is counted by intervalcounter 320, may be changed periodically. The reset signal 316 restartsthe synch count.

Once interval counter 320 completes the synch count, a skew interval 322receives a signal indicating that the time interval for substantiallysynchronous behavior of the asynchronous interface has expired. Inresponse to the signal, skew interval 322 transmits a signal 326 todelay generator 330 and possibly to other delay generators for other bitlines associated with the same bus or another bus.

Delay generator 330 comprises random logic 332 and multiplexor 334.Random logic 332 may generate a substantially random selection signalfor multiplexor 334. In some embodiments, the selection signal generatedby random logic 332 may be selected from equally weighted selectionsignals. In other embodiments, the selection signals may be weighteddifferently.

The selection signal may comprise one or more bits and multiplexor 334may select an input from delay applicator 340 based upon the selectionsignal. The selection of an input from delay applicator 340 in thisembodiment selects a bit that is delayed by a skew. In many embodiments,each input from delay applicator 340 may comprise the bit delayed by adifferent skew and the skews may range, e.g., from a zero skew to amaximum skew for the corresponding bit line of the asynchronous bus. Infurther embodiments, a zero skew option may not be available so theskews may vary from a minimum skew to a maximum skew. In still otherembodiments, the minimum skew available may be less than a zero skew ora negative skew, depending upon parameters of the simulation, timereferences selected for the latches, or evaluative tools for the logic.

Random logic 332 maintains the same signal at the input of multiplexor334 until a signal is received from synch counter 310 to generate asubsequent selection signal. Then, the subsequent selection signal maybe the same or different from the prior selection signal in someembodiment. As a result, delay generator 330 selects the same skew forsubsequent bits until random logic 332 generates a new selection signal.

Delay applicator 340 may receive a bit of bit line data and apply anumber of different delays to the bit. Each delay, which is within aselected range of skews for the bit line, is input into multiplexor 334.To illustrate the present embodiment, assume that latches 342 through348 each add a one clock cycle delay to a bit received at the bit linedata input of latch 342. In other words, the bit is propagated latch tolatch toward latch N through the latches. Selection of the output oflatch 342 via multiplexor 334 provides the bit with a one clock cycleskew. Similarly, the output of latch 344 provides a two cycle delay, theoutput of latch 346 provides a three cycle skew, and the output of latch348 provides an N cycle skew. Latch 350, if enabled via the enableinput, provides the bit line data with a zero cycle skew as an input tomultiplexor 334.

FIG. 4 illustrates an embodiment of a staged multiplexor 400 to equatethe probabilities for selection of a skew from a set of seven differentpotential skews 405, 425, and 440 to model the behavior of a bit line ofan elastic interface. Staged multiplexor 400 or another stagedmultiplexor may be implemented in place of multiplexor 334 of FIG. 3 tohandle a number of inputs received from delay applicator 340 of FIG. 3that is not a power of two.

Multiplexor (MUX) 420 receives four inputs 405 from, e.g., a delayapplicator and two selection signals 410 and 415 from, e.g., a randomlogic. The selection signals each have an equal chance “1/1” of being alogical one or a logical zero. “1/1” represents the weighting of alogical zero and a logical one.

Similarly, MUX 435 selects between two inputs 425. Selection signal 430provides a 50% chance of being a logical zero and a 50% chance of beinga logical one as indicated by “1/1”. Then, the selected outputs of MUX420 and MUX 435 are input into MUX 450. MUX 450 receives a selectionsignal 445 that has a one in three chance “1/3” of selecting a logicalzero over a logical one and, as a result, provides equivalentprobabilities of selecting each of the inputs 405 and 425.

After selecting from inputs 405 and 425, the selected input is appliedto an input of MUX 460. The seventh possible input 440 is also appliedto an input of MUX 460. MUX 460 then receives a selection signal 455that provides a one in seven chance “1/7” of selecting the input 440.The selected input from the seven inputs is then sent to other logic viaoutput 465.

Referring now to FIG. 5, there is shown a flowchart of an embodiment tosimulate synchronous and asynchronous behavior of bit lines of anasynchronous bus. Flow chart 500 begins with resetting a time intervalcount, or synch count, in response to sending test pattern data (element510). For example, during initialization of a time interval ofsubstantially synchronous data transfer on the asynchronous bus, testpattern data is transmitted across the bus to determine a skew patternfor data crossing the bus. As the test pattern data is transmittedacross the bus, the time interval count down for substantiallysynchronous behavior is restarted.

A counter may decrement the time interval count each clock cycle(element 515) until the interval expires (element 520). Once the timeinterval count reaches zero, the counter signals logic to generate arandom select signal (element 525), which is applied to a select inputof, e.g., a multiplexor, a multi-stage multiplexor, or similar logic.The multiplexor may then select a skew for a bit line of theasynchronous bus based upon the random select signal (element 530). Forexample, the multiplexor may comprise several inputs for the bit andeach input may add a different amount of delay or skew to transmissionof the bit across the asynchronous bus. The random select signal maythen facilitate selection of one of those skews in a substantiallynon-deterministic manner. In other embodiments, selection of one ofthose skews may follow a heuristic or other dynamic or pre-determinedpattern. Then, when the time interval for substantially synchronousbehavior expires, the multiplexor receives a new select signal to modifythe skew pattern again in a substantially non-deterministic manner,advantageously modeling the behavior of the time-constrained,asynchronous bus.

If there are additional bit lines of the bus (element 540), asubstantially non-deterministic skew may be selected for each bygenerating random select signals (element 525), selecting skews for eachbased upon the random select signals (element 530), and applying theskews to data crossing the bit lines of the bus (element 535).Furthermore, if the circuit simulation is to continue (element 545),each element of flowchart 500 from element 510 to element 540 may berepeated. Otherwise, the circuit simulation may end.

Another embodiment of the invention is implemented as a program productfor implementing a circuit simulation such as circuit simulation 100illustrated in FIG. 1. The program(s) of the program product definesfunctions of the embodiments (including the methods described herein)and can be contained on a variety of data and/or signal-bearing media.Illustrative data and/or signal-bearing media include, but are notlimited to: (i) information permanently stored on non-writable storagemedia (e.g., read-only memory devices within a computer such as CD-ROMdisks readable by a CD-ROM drive); (ii) alterable information stored onwritable storage media (e.g., floppy disks within a diskette drive orhard-disk drive); and (iii) information conveyed to a computer by acommunications medium, such as through a computer or telephone network,including wireless communications. The latter embodiment specificallyincludes information downloaded from the Internet and other networks.Such data and/or signal-bearing media, when carrying computer-readableinstructions that direct the functions of the present invention,represent embodiments of the present invention.

In general, the routines executed to implement the embodiments of theinvention, may be part of an operating system or a specific application,component, program, module, object, or sequence of instructions. Thecomputer program of the present invention typically is comprised of amultitude of instructions that will be translated by a computer into amachine-readable format and hence executable instructions. Also,programs are comprised of variables and data structures that eitherreside locally to the program or are found in memory or on storagedevices. In addition, various programs described hereinafter may beidentified based upon the application for which they are implemented ina specific embodiment of the invention. However, it should beappreciated that any particular program nomenclature that follows isused merely for convenience, and thus the invention should not belimited to use solely in any specific application identified and/orimplied by such nomenclature.

It will be apparent to those skilled in the art having the benefit ofthis disclosure that the present invention contemplates methods andarrangements to model behavior of an asynchronous interface. It isunderstood that the form of the invention shown and described in thedetailed description and the drawings are to be taken merely asexamples. It is intended that the following claims be interpretedbroadly to embrace all the variations of the example embodimentsdisclosed.

Although the present invention and some of its advantages have beendescribed in detail for some embodiments, it should be understood thatvarious changes, substitutions and alterations can be made hereinwithout departing from the spirit and scope of the invention as definedby the appended claims. Although an embodiment of the invention mayachieve multiple objectives, not every embodiment falling within thescope of the attached claims will achieve every objective. Moreover, thescope of the present application is not intended to be limited to theparticular embodiments of the process, machine, manufacture, compositionof matter, means, methods and steps described in the specification. Asone of ordinary skill in the art will readily appreciate from thedisclosure of the present invention, processes, machines, manufacture,compositions of matter, means, methods, or steps, presently existing orlater to be developed that perform substantially the same function orachieve substantially the same result as the corresponding embodimentsdescribed herein may be utilized according to the present invention.Accordingly, the appended claims are intended to include within theirscope such processes, machines, manufacture, compositions of matter,means, methods, or steps.

1. A method to model behavior of an asynchronous interface, the methodcomprising: generating a first pattern of skews for a number of bitlines of the asynchronous interface; applying the first pattern of skewsto bits associated with the number of bit lines during a time interval;and applying a second pattern of skews to subsequent bits associatedwith the number of bit lines after the time interval.
 2. The method ofclaim 1, further comprising determining a skew pattern between thenumber of bit lines based upon comparison between bits of a test patternand a pattern of received bits.
 3. The method of claim 1, furthercomprising counting clock cycles of the time interval and resetting thetime interval upon transmission of a test pattern of bits.
 4. The methodof claim 1, wherein generating the first pattern comprises generating aselection signal for a multiplexor logic to select a skew for at leastone of the bit lines.
 5. The method of claim 4, wherein generating thefirst pattern comprises selecting the skew from a set of skews via themultiplexor logic based upon the selection signal, wherein a probabilityof selection of the skew from the set of skews is predetermined.
 6. Themethod of claim 1, wherein applying the first pattern comprises applyingthe first pattern prior to transmission of data across the asynchronousinterface.
 7. The method of claim 1, wherein applying the first patterncomprises applying the first pattern upon receipt of data at a receiverfrom the asynchronous interface.
 8. The method of claim 1, whereinapplying the second pattern of skews comprises generating the secondpattern of skews.
 9. The method of claim 7, wherein generating thesecond pattern of skews comprises selecting skews for each of the numberof bit lines in a substantially non-deterministic manner.
 10. A systemto model behavior of an asynchronous interface, the system comprising: adelay applicator to apply skews to bits crossing the asynchronousinterface via a number of bit lines; and a delay generator to generate afirst pattern of the skews for the number of bit lines during a timeinterval and to generate a second pattern of skews for subsequent bitscrossing the asynchronous interface via the number of bit lines afterthe time interval.
 11. The system of claim 10, further comprising asynch counter to count clock cycles of the time interval to indicate anend of the time interval and to restart the time interval upontransmission of test pattern data.
 12. The system of claim 10, whereinthe delay applicator comprises delay logic to apply the skews prior totransmission of the bits across the asynchronous interface.
 13. Thesystem of claim 10, wherein the delay applicator comprises delay logicto apply the skews after receipt of the bits from the bit lines.
 14. Thesystem of claim 11, wherein the delay generator couples with the synchcounter to generate the second pattern of skews upon expiration of thetime interval, wherein the second pattern of skews is substantiallynon-deterministic.
 15. The system of claim 10, wherein the delaygenerator comprises random logic to generate a selection signal for amultiplexor logic to select from the skews applied to the bits crossingthe asynchronous interface for at least one of the bit lines.
 16. Thesystem of claim 15, wherein the delay generator comprises themultiplexor logic to select from the skews applied to the bits crossingthe asynchronous interface based upon the selection signal, wherein aprobability of selection of a skew from the skews is predetermined. 17.The system of claim 15, wherein the multiplexor logic is adapted toindependently select a skew from the skews for each of the number of bitlines.
 18. A machine-accessible medium containing instructions to modelbehavior of an asynchronous interface, which when the instructions areexecuted by a machine, cause said machine to perform operations,comprising: generating a first pattern of skews for a number of bitlines of the asynchronous interface; applying the first pattern of skewsto bits associated with the number of bit lines during a time interval;and applying a second pattern of skews to subsequent bits associatedwith the number of bit lines after the time interval.
 19. Themachine-accessible medium of claim 18, wherein the operations furthercomprise counting clock cycles of the time interval and resetting thetime interval upon transmission of a test pattern of bits.
 20. Themachine-accessible medium of claim 18, wherein the operations furthercomprise determining a skew pattern between the number of bit linesbased upon comparison between bits of a test pattern and a pattern ofreceived bits.